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Computer Architecture & Organization GNDU PU PTU LPU Ebook Lecture Notes pdf Download|Anand Technical Publishers|Neeraj K Anand — PARAM ANAND

 

Bachelor of Computer Applications (Semester III)

Paper I: Computer Architecture
Time: 3 Hours M. Marks: 75
Note:
1. In theory eight questions are to be set in all. The candidates are required to attempt five of them. All questions are to be of equal marks. The maximum marks of the paper is 75.
2. The student can use only Nonprogrammable & Nonstorage type Calculator.


UNITI
Information Representation : Register Transfer, Various Registers, Implementing Common Bus Using Multiplexers: Logical; Arithmetic & Shift Micro operations.
Basic Computer Design Instruction Codes, Interfacing various Registers, Computer Instructions, Timing Signals, Instruction Cycle, Design of a Basic Computer.
UNITII
CPU Design Stack Organized CPU, Instruction Formats, Addressing Modes, Program Control, Hardwired & Microprogrammed (Wilhe’s Design) Control Unit.
Memory Organization Memory Hierarchy, Designs & Concepts of Main Memory, Auxiliary Memory, Associative Memory, Cache and Virtual Memory.
UNITIII
I/O Organization I/O Interface, Modes of Transfer, Program Interrupt, DMA & I/O Processor.
Pipeline & Vector Processing Parallel Processing Pipelining, Parallel & Distributed Computers, SISD, SIMD & MISD, MIMD Machines, Vector Processing.

 

CSA1: B.TECH. (COMPUTER SCIENCE & ENGINEERING) SEMESTER III

(Under Credit Based Continuous Evaluation Grading System)
CSL230: COMPUTER ARCHITECTURE

CREDITS
L T P
3 1 0
UNITI
Principles of computer design software / hardware interaction, cost/benefit concept of layers in architecture design. [10%]
Basic Computer Organization taking 8085 as an example binary arithmetic – add, subtract, multiply – algorithms and implementations. Carry look ahead add fast adders. [15%]
CPU design Choice of instruction set control structure hardwired and microprogrammed control RISC vs. CISC, Pipelining in CPU design superscalar machines. [15%]
UNIT II
Memory hierarchy design caches, main memory, interleave memory, virtual memory
architectural aids in implementing these. [10%]
I/O Modes Program interrupt, DMA, Channel, I/O Processor. [15%]
UNITIII
I/O Performance measures Buses connecting I/O devices to CPU/memory interaction with operating system Serial/Parallel interfaces taking 8251 and 8255 as example. [15%]
Performance evaluation SPEC marks LINPACK Whetstone Dhrystone etc., Transaction
processing benchmarks. [10%]
Multiprocessors – Parallel & distributed computers – SIMD SPMD and MIMD machines.
[10%]

 

Bachelor of Technology
Computer Science Engg.
(Artificial Intelligence & Machine Learning)

Course Code: BTES401-18 Course

Title: Computer Organization & Architecture

Pre-requisites: Digital Electronics
Detailed Contents:

Module 1: Functional blocks of a computer

CPU, memory, input-output subsystems, control unit. Instruction set architecture of a CPU registers, instruction execution cycle, RTL interpretation of instructions, addressing modes, instruction set. Case study instruction set of 8085 processor.

Data representation: signed number representation, fixed and floating point representations, character representation. Computer arithmetic integer addition and subtraction, ripple carry adder, carry look-ahead adder, etc. multiplication shift-andadd, Booth multiplier, carry save multiplier, etc. Division restoring and non-restoring techniques, floating point arithmetic.

[10 hrs] (CO1, CO2)

Module 2: Introduction to x86 architecture.

CPU control unit design: Hardwired and micro-programmed design approaches,
Case study – design of a simple hypothetical CPU.

Memory system design: semiconductor memory technologies, memory organization.
Peripheral devices and their characteristics: Input-output subsystems, I/O device interface,
I/O transfers program controlled, interrupt driven and DMA, privileged and non-privileged instructions, software interrupts and exceptions. Programs and processes role of interrupts in process state transitions, I/O device interfaces SCII, USB.

[12 hrs] (CO2, CO4)

Module 3: Pipelining

Basic concepts of pipelining, throughput and speedup, pipeline hazards.

Parallel Processors: Introduction to parallelprocessors, Concurrent access to memory and cache coherency.
[10 hrs] (CO5)
Module 4: Memory Organization

Memory interleaving, concept of hierarchical memory organization, cache memory, cache
size vs. block size, mapping functions, replacement algorithms, write policies.
[10 hrs] (CO3)
Course Outcomes:

The student will be able to:

1. Understand functional block diagram of microprocessor;

2. Apply instruction set for Writing assembly language programs;

3. Design a memory module and analyze its operation by interfacing with the CPU;

4. Classify hardwired and microprogrammed control units; &

5. Understand the concept of pipelining and its performance metrics.

I. K. Gujral Punjab Technical University
Bachelor of Computer Applications (BCA)

Detailed Contents
UnitI

Logic Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR, NAND & NOR
as Universal Gates, Logic Gates Applications.[CO5]

Boolean Algebra: Introduction, Theorems, Simplification of Boolean
Expression using Boolean Algebra, SOP & POS Forms, Realization of
Boolean Expression using Gates, KMaps, Simplification of Boolean
Expression using KMaps. [CO2]

UnitII
Combinational Logic Circuits: Half Adder & Half Subtractor, Full Adder &
Full Subtractor, Parallel Binary Adder, Binary Adder/Subtractor. [CO4]

Combinational Logic Circuits: Multiplexers & Demultiplexers, Implementation of Boolean equations using Multiplexer and Demultiplexer, Encoders & Decoders.

UnitIII
Sequential Logic Circuits: Latch, Flip Flops RS FlipFlop, JK FlipFlop,
Race Around Condition, Removing Race Around Condition, MasterSlave JK FlipFlop, D FlipFlop, T FlipFlop, Applications of FlipFlops. [CO3]

UnitIV

Introduction to Computer Organization: Introduction to Computer and
CPU (Computer Organization, Computer Design and Computer Architecture), Stored Program Concept Von Neumann Architecture, Harvard Architecture, RISC and CISC Architecture. [CO1]

Register Transfer and Micro operations Introduction to Registers, Instruction Format, Types of Instructions Memory Reference Instructions, Register Reference Instructions and InputOutput Instructions.

Common Bus System: Introduction to Common Bus System, Types of Buses  (Data Bus, Control Bus, Address Bus), 16bit Common Bus SystemData Movement among registers using Bus.[CO4]

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